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If it doesn't work in simulation then you're clearly doing something wrong. If you drill down into the RAM in simulation what do you see during writes? Does everything look right at that level? There are only a few signals involved here so it's got to be a simple problem.
Any synthesis warnings that might explain it?
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I've never been able to get the ram to show data in simulation, its outputs are always Z. The input signals appear correct in simulation though, and on hardware the read functions correctly. I can't launch modelsim from quartus since it says the path is wrong even though it's correct, so it's probably not simulating the ram correctly anyway.
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