New Contributortriple speed ethernet on cyclone V E development board
hello,
i am using Cyclone V E development board which include 5cefa7f31i7n chip and quartus version 15 web edition.
i want to learn how to implement bare TSE IP without nios softcore processor. i want to implement it with VHDL.
firstly, i generated a TSE IP on QSYS and place it in block and Schematic. I assigned pin numbers and wrote a vhdl which include signals for TSE IP control port signals with using TSE IP USER GUIDE.
my problem is starting at the control port signals. in the control port signals, there is a waitrequest (reg_busy) signal. it asserts when register read and write access to the TSE and deasserts when their access is completed.
I controlled these signals with the signal tap analyzer. reg_busy signal is always '1' so i could not write mac_data bits on IP.
how can i solve this problem or is there any tutorial or hint for implementing bare TSE IP with hardware configuration. My target is, i only use TSE IP and on chip memory between 2 fpga ethernet port and communicate them in a simple way.
thank you for supports!
