Triple Speed Ethernet MII/GMII - Timing Issue

When I send a UDP Broadcast packet from the PC to the board, the packet is

visible on the GMII RX lines coming from PHY. But data do only sporadically arrive on the Avalon-ST RX bus - see post TSE GMII gmii_rx_dv without data_rx_valid signal

The behaviour depends on the synthesis - without logic reference. Sometimes it works, sometimes it doesn't work and I have to resynthesise. This is annoying, so I would like to have a consistent solution to the problem.

The FPGA C10GX200 with the MAC TSE IP Core is connected to a PHY KSZ9031MNX.
Fifoless TSE MAC without Nios.
For the KSZ9031MNX PHY the GMII receive timing - data input to MAC is given as follows:

I understand that the phy applies the data on the falling rx_clock edge. Correct?
Or do I have to take care of this delay myself for the incoming data in the FPGA?

I have tried around with the following instructions and different delay times in the sdc file of the project. There seems to be an influence on the behaviour described above, but maybe that's just coincidence, because the problem still occurs in a synthesis-dependent way.

set_input_delay -clock rx_clk -rise 2.000 eth_rx_dv
set_input_delay -clock rx_clk -rise 2.000 eth_rx_err
set_input_delay -clock rx_clk -rise 2.000 eth_rxd[*]

I found the sdc file attached (altera_eth_tse_fifoles_mac.sdc) in the directory of the TSE IP core, but I don't quite understand what it does and whether it has an effect on my problem.

Unfortunately, there is very little information about timing in the TSE IP Core documentation.

Is there a more detailed instruction for this somewhere?
What does the timing have to look like so that the TSE IP Core reliably outputs the received data to the Avalon-ST bus?