Triple Speed Ethernet Dual MII/GMII

Hi,

Has anyone out there used the Altera TSE Ethernet core to connect to a 10/100/1000 Phy device on a custom board?

We're developing a board and FPGA to support this function and are pin limited on the FPGA and would like to share the pins for GMII and MII operation (This is easily done at a board level).

When I generate the TSE it populates two full interfaces , one for MII and one for GMII. So the question is can I multiplex these signals internally to the FPGA and just present a GMII interface externally (ie share the data pins and control pins).

It would seem to be a simple and sensible thing to do but just wondered if there's anything I'm missing here !! (Indeed why the TSE generates two full interfaces anyway ...)

Thanks

Paul

Paul