to use altlvds,how I can use LVDS bit clock and LVDS frame clock of ADC at the same t

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"2, In the following sentence, "The final piece is to write a fairly simple state machine to pulse rx_channel_data_align", what does "pulse" mean? Keep rx_channel_data_align to 1 all the time?"

Pulse here mean a high and low signal instead holding the signal at high always. In other words, in your control, you assert it for certain clock cycle and then de-assert it.

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Thanks for your answer, bfkstimchan.

First, I assert rx_channel_data_align, after I receive the right data, I should de-assert the rx_channel_data_align, is my understanding correct?