timing_violations_onddr3_and_jtag

Question

Hi Team,

I have compiled the design which comprises of nios ii , ddr3 and avalon mm other interfaces.

I am getting timing violations. Can you please guide me to resolve this? attached the timing report summary

sstrell · Answer

https://www.intel.com/content/www/us/en/support/programmable/articles/000092769.html

tingjiangt_intel · Answer

Please help to show the violation message in Timing analyzer.

sermaswathika · Answer

Hi ,i am getting negative slack on pll_afi_clock of ddr3 memoryshall i add false path for that violation?PLease give suggestion

tingjiangt_intel · Answer

Is this setup violation or hold violation?And please using 'report timing' to check and show the path details, thanks.

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