Timing Violation for legacy DDR2 Controller

But from the controller document, I can see "When we compile a project after generating or editing and re-generating the variation, the auto_add_ddr_constraints.tcl script automatically calls the constraints script specific to each instance of the controller in the design". So I did not feel any necessity of running the script after generating the variation.

The input frequency for the PLL is 80 MHz. So I edit the pll parameters and did the compilation. There was no warning. But when I edited the pin locations as per the board we have. It failed timing analysis. So I would like to know, what else steps are to be taken after we edit the pin assignments as per our requirement.

For your reference, I am using the following pin assignment for the Stratix II GX device

PPC2_DDRACLK0 AJ11

PPC2_DDRACLK1 AL11

PPC2_DDRAADD0 AJ12

PPC2_DDRAADD10 AL12

PPC2_DDRAADD11 AG14

PPC2_DDRAADD12 AC13

PPC2_DDRAADD13 AD13

PPC2_DDRAADD2 AF11

PPC2_DDRAADD3 AH11

PPC2_DDRAADD4 AM12

PPC2_DDRAADD5 AG13

PPC2_DDRAADD6 AP13

PPC2_DDRAADD7 AL14

PPC2_DDRAADD8 AH12

PPC2_DDRAADD9 AE11

PPC2_DDRABA0 AM11

PPC2_DDRABA1 AG11

PPC2_DDRACONTROLT0 AF10 WE# O

PPC2_DDRACONTROLT1 AG10 RAS#

PPC2_DDRACONTROLT2 AE9 CAS# O

PPC2_DDRACONTROLT3 AP7 CS# O

PPC2_DDRACONTROLT4 AM7 DQS# O

PPC2_DDRACONTROLT5 AL7 DQS O

PPC2_DDRACONTROLT6 AL8 RDQS O

PPC2_DDRADATAT0 AG8 Data Pin

PPC2_DDRADATAT1 AN8 Data Pin

PPC2_DDRADATAT2 AM8 Data Pin

PPC2_DDRADATAT3 AJ8 Data Pin

PPC2_DDRADATAT4 AK8 Data Pin

PPC2_DDRADATAT5 AJ7 Data Pin

PPC2_DDRADATAT6 AP8 Data Pin

PPC2_DDRADATAT7 AH7 Data Pin