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Altera_Forum's avatar
Altera_Forum
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15 years ago

Timing requirements not met for HPCII example design

Hello, I'm testing out the DDR2 high performance controller II, but when compiling the example design, the timing requirements are not met. The critical path is through a PLL deep in the megafunct...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

OK, thanks again!

The example design seems to run okay at 300MHz as well, although TimeQuest still reported some timing issues.. It might be best to run it slower to be absolutely sure. But the PNF signal stays asserted all the time. No wonder why the test_complete led never lights, because this is only a pulse between the read/write tests.

Not using dev kits: respect! :-)