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Altera_Forum
Honored Contributor
Honored ContributorTiming requirements not met for HPCII example design
Hello, I'm testing out the DDR2 high performance controller II, but when compiling the example design, the timing requirements are not met. The critical path is through a PLL deep in the megafunct...
Altera_ForumHonored Contributor
Honored ContributorPassNotFail, I remembered.
I am not that familiar with the Arria II GX devkit, actually I almost never use devkits. (unless to learn from the schematic ...) According to the documentation the C5 speed grade can handle a 333 MHz half rate design but with a 400MHz DDR2 device.
