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Altera_Forum's avatar
Altera_Forum
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15 years ago

Timing requirements not met for HPCII example design

Hello, I'm testing out the DDR2 high performance controller II, but when compiling the example design, the timing requirements are not met. The critical path is through a PLL deep in the megafunct...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thank you, the timing is closed using half-rate, but I also had to reduce the memory frequency to 200 MHz. I also found out my device is speed grade 5 :P

However, when running the example_top design on the hardware, the test_complete signal stays deasserted. I would think this is due to some board timing specifications, but I cannot find any such specifications in the documentation that came with the kit (Arria II GX dev kit). Do you know where I could find these? That would've been awesome :). Also, do you know what the pnf and pnf_per_byte signals in the example top is?

I should probably do some signal-tapping... :)