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Altera_Forum's avatar
Altera_Forum
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15 years ago

Timing requirements not met for HPCII example design

Hello, I'm testing out the DDR2 high performance controller II, but when compiling the example design, the timing requirements are not met. The critical path is through a PLL deep in the megafunct...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I searched a bit deeper in the documentation and found the 333 MHz performance for the Arria II GX in half-rate mode. However, you selected a full-rate controller with a half rate bridge enabled. I have no idea whether this is interpreted as 'full' or as 'half'. Maybe you better select plain 'half' rate controller.