Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorTiming requirements not met for HPCII example design
Hello, I'm testing out the DDR2 high performance controller II, but when compiling the example design, the timing requirements are not met. The critical path is through a PLL deep in the megafunct...
Altera_ForumHonored Contributor
Honored ContributorAn Arria II GX -4 device will only go up to 267 MHz in half-rate mode.
