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Altera_Forum
Honored Contributor
Honored ContributorTiming requirements not met for HPCII example design
Hello, I'm testing out the DDR2 high performance controller II, but when compiling the example design, the timing requirements are not met. The critical path is through a PLL deep in the megafunct...
Altera_ForumHonored Contributor
Honored ContributorSome more information about the problem:
Timing is violated in the Phy part of the controller. It is the setup time that is violated. The clock source is the auto-generated PLL mentioned above. Megafunction parameters: Device familiy: Arria II GX Speed grade: 4 PLL reference clock freq: 100 MHz Memory clock frequency : 333.333 MHz Controller data rate: full, with half rate bridge enabled Memory preset: Micron MT8HTF12864HY-800 @ 333 MHz Using differential DQS Address/command clock phase: 90 degrees Board settings: default altera settings, with 1 slot Controller settings: High performance controller II Rest here is default I'm using the Arria II GX development kit. All signals to/from the SODIMM are placed on the bottom I/O banks, as well as the 100MHz clock source. Any help would be greatly appreciated :-)
