Forum Discussion
Altera_Forum
Honored Contributor
8 years agoIf you mean conf_reg is constant then that is not a timing path to reg (a).
Now if reg (a) is on slow clk you are sampling a constant (no problem) and (a) will acquire new value. If this is passed to fast clock then this path from (a) must be allowed to settle. You need to explain clocks used in your request of a <= conf_reg