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Altera_Forum
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9 years ago

timing questions -false path for the experts

Hi, I have a design that has value in it that define the code behavior, let call them: config_reg table_of_vaule 1. because of the nature of those things, they are deep in the design. ...
Altera_Forum's avatar
Altera_Forum
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9 years ago

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Can we assume a<=config_reg will be valid, asume config_reg does not change?

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For clock crossing there are two scenarios:

If any signal transition from clk1 domain to clk2 domain is designed to be sampled after several clocks periods on clk2 then it is safe. This implies slow signals

For faster signals (as well as short pulses) , above cannot be done and a fifo (or handshake) solution is needed.