timing questions -false path for the experts

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Can we assume a<=config_reg will be valid, asume config_reg does not change?

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For clock crossing there are two scenarios:

If any signal transition from clk1 domain to clk2 domain is designed to be sampled after several clocks periods on clk2 then it is safe. This implies slow signals

For faster signals (as well as short pulses) , above cannot be done and a fifo (or handshake) solution is needed.