Altera_Forum
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16 years agoTiming fails with two TSE MACs
Hi everyone,
I'm working on a DBC3C40 board and I'm building a system based on the TripleSpeedEthernet sample. I need to use both Ethernet PHYs available on the board, so I added a second TSE MAC in SOPC with all the other required interfaces. The problem is that I obtain a timing critical warning: "Timing requirements for slow timing analysis were not met" In the detailed report I see the problem is due to clock hold for pll1: slack=-2.345ns, required time=50MHz(20ns) I tried to route the clock nets in a different way, for example: - driving the second MAC clock with another pll output - using another clock pin and pll for driving the second MAC, or even both In any case the clock hold delay slightly changes but I always have a timing failure. The final result is that the Nios software doesn't work: usually it recognizes the Ethernet link but then everything gets stuck just when I start sending data over the Ethernet port; sometimes neither the Ethernet link can be established. Thank you for any help Regards