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anonimcs's avatar
anonimcs
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2 years ago

Timing constraints of Intel IPs

Hi all, I have a design on Quartus 21.3 Pro and I noticed that the External Memory Interface IP for DDR4 memory has some timing violations within the IP core. I would expect that these kind of IP co...
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RichardT_altera's avatar
RichardT_altera
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1 year ago

Hi,

It seems the failure path is from the peripheral to the core.

You can open QSYS interconnect and check whether it is feasible to add a pipeline to the timing failing path. Please see the example below, as shown in the attachment.

Regards,

Richard Tan

anonimcs's avatar
anonimcs
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1 year ago
@RichardTanSY_Altera wrote:

Hi,

Please see the example below, as shown in the attachment.

Which attachment, and which example ?

And the failing path is from the IP to the interconnect, how am I supposed to add something inbetween ? It will end up with the same error as I'll connect the IP to another component in the Platform Designer for pipelining the failing signal...