TI EMIF Avalon Master

Thanks for the hints. We did design the component using a HDL-file which we imported in the component editor. The signals in the interface follows the convention so the editor knows what's in the conduit, master and cleck/reset. It worked out really well, and we have done the first run in ModelSim using this component along with a PIO. All successful!

Many thanks for the qucik and good reply. I have attached the code if you're interested. The glue logic might change, cosnider it as a basic setup to get things in the right place and right order.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

library altera;

use altera.altera_europa_support_lib.all;

library std;

use std.textio.all;

entity EMIF_Bridge is

port (

-- The EMIF interface (conduit)

--signal cos_emif_eclkout : IN STD_LOGIC;

--signal cos_emif_eclkin : OUT STD_LOGIC;

signal cos_emif_ed : INOUT STD_LOGIC_VECTOR (31 DOWNTO 0);

signal cos_emif_ea : IN STD_LOGIC_VECTOR (21 DOWNTO 2);

signal cos_emif_ce_n : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

--signal cos_emif_be_n : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

signal cos_emif_aoe_n : IN STD_LOGIC;

signal cos_emif_are_n : IN STD_LOGIC;

signal cos_emif_awe_n : IN STD_LOGIC;

--signal cos_emif_hold_n : OUT STD_LOGIC;

--signal cos_emif_holda_n : IN STD_LOGIC;

--signal cos_emif_busreq : IN STD_LOGIC;

-- Global clock and reset

signal csi_clk : IN STD_LOGIC;

signal csi_reset_n : IN STD_LOGIC;

-- The Avalon-MM master interface (to the fabric)

signal avm_m0_address : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

signal avm_m0_read_n : OUT STD_LOGIC;

signal avm_m0_waitrequest : IN STD_LOGIC;

signal avm_m0_readdata : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

signal avm_m0_write_n : OUT STD_LOGIC;

signal avm_m0_writedata : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)

);

end entity EMIF_Bridge;

architecture InterfaceLogic of EMIF_Bridge is

begin

avm_m0_address(31 downto 0) <= "000000000000" & cos_emif_ea(21 DOWNTO 2);

avm_m0_read_n <= cos_emif_are_n;

avm_m0_write_n <= cos_emif_awe_n;

tristate_control: process(csi_clk)

begin

if rising_edge(csi_clk) then

if cos_emif_aoe_n = '1' then

cos_emif_ed(31 DOWNTO 0) <= (others => 'Z'); -- Never drive bus when output enable is inactive from DSP

-- Decode DSP write access to Avalon-MM master

if (cos_emif_ce_n(0) = '0' OR cos_emif_ce_n(1) = '0' OR cos_emif_ce_n(2) = '0' OR cos_emif_ce_n(3) = '0') THEN

avm_m0_writedata(31 DOWNTO 0) <= cos_emif_ed(31 DOWNTO 0);

end if;

else

-- Decode DSP read access from Avalon-MM master

cos_emif_ed(31 DOWNTO 0) <= avm_m0_readdata(31 DOWNTO 0);

end if;

end if;

end process tristate_control;

end architecture InterfaceLogic;

So we are on track I believe, and all looks good! :)

/Andreas