Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Three Wire SPI connection question

Hi all,

Here is a breif description of my particular issue.

I am working on a system that contains a Cyclone III FPGA. One of the peripherals the FPGA needs to manage is an Analog Devices ad9629-40 adc (http://www.analog.com/static/imported-files/data_sheets/ad9629.pdf).

This particular part allows for configuration via a SPI interface. The ADC does not use 4 pins to support the standard SPI signals (sclk, ss, mosi, miso). There is a single pin (pin 6 on the data sheet linked above) that is used for bidirectional communication, or for both the miso/mosi signals. In short, you start by writing an instruction to the ADC (the pin starts out in the mosi state), and based on the instruction, the pin assumes either the mosi or the miso state in subsequent phases of communication with the device.

Being new to FPGA development, I have been relying on altera IP in SOPC builder to get a base FPGA system created. The standard SPI IP block available in SOPC builder has the four standard SPI signals defined as you would expect. I am not sure if the SPI IP block can be used to communicate with this ADC as the ADC has two of those signals combined. I am not sure how I would go about connecting that at the very least.

Any ideas on how I should proceed?

Regards,

Seth

P.S. I did attempt to find existing threads on this topic, but none were helpful. If I missed relevant threads in my search please let me know - I'd be glad to read them ;)

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    As an optimal solution, you would build the output enable control for the bidrectional pin into your SPI interface. It can switch the direction after 16 clocks depending on the R/W bit.If you don't want to do this, you have two options:

    -operate the SDIO line with a pull-up resistor and an open drain driver. You have to write 0xFF to the SPI bus during read phases

    -implement an additional R/W control signal that enables the driver and set it to "read" in the middle of a SPI read transaction. This should work, because the SOPC SPI interface is using 8-Bit entities.