the waitrequest of avalon bus

If the waitrequest is output of a flip flop, when use the avalon bus transfer the data to the FIFO,there is a data cann't be stored. For example,when the data2 sampled by the FIFO,there is no space and full pull up,at next cycle the full signal will be sampled and the next cycle waitrequest will be pull up.that means data3 will be losed.

If the waitrequest output with the combinational logic,there is no problem,when the full pull up,the waitrequest will pull up at the same cycle. but the output delay of waitrequest will be increased, it's bad for synthsis.

thank you!