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Hi:
the output shoud use the register many paper write that,but I find that if the waitrequest output with register will lead to delay a
cycle.it is difficult to design the register timing.if use the combinational logic will solve the problem.but I am not sure whether it is reliable.
thank you!
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Typically, one can design the wait request output to be the output of a flip flop, but it is not a requirement. There is nothing unreliable about using combinatorial logic.
If you're having difficulty with the output being a flop and would like it to be one, then take note that the wait request output is a don't care while the read/write controls are inactive. This implies that wait request can be a 1 during those times. That way, on the clock cycle when read or write changes to a 1, wait request will already be set to 1 to give you the wait cycle that you need. Once you're ready to release wait request you clear it for the next clock cycle.
If you have a more specific question, ask.
Kevin Jennings
Honored Contributor
