The Use of Seriallite II protocol in Arria II GX series

Regarding the use of the Seriallite II protocol in hardware: The chip we use is the EP2AGX65DF29C6N of the Arria II GX series. When using quartus II to allocate the pins, it is not clear how the input and output of the Seriallite II IP core should be connected to the chip pins.

Regarding the pin connection, the specific problem is this: On the SLII IP, there are data input and output pins, such as rxin, txout, rxrdp_dat[], txrdp_dat[], etc., as well as some other signal pins (with bsf attached).

And on the FPGA chip we use (with pin diagram attached), there are ten banks, of which there are two GXB banks, divided into general purpose I/O, high-speed differential I/O, high-speed differential I/O with DPA, and we also want to use LVDS.

Therefore, we want to find out which bank or IO port these signals on the SLII IP should be connected to, and whether you have any other opinions and suggestions on the use of LVDS in this process.

Hereby ask for help, hoping to solve the problem.