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shan039031's avatar
shan039031
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4 years ago

The Use of Seriallite II protocol in Arria II GX series

Regarding the use of the Seriallite II protocol in hardware: The chip we use is the EP2AGX65DF29C6N of the Arria II GX series. When using quartus II to allocate the pins, it is not clear how the inpu...
shan039031's avatar
shan039031
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4 years ago

Thank you for your reply.

I have read the two documents you sent. They are all about FPGAs, but our problem is mainly that we want to use the Seriallite II IP core and cannot confirm the connection between the signal and the FPGA pins. We are worried that the chip will be damaged during use, So I want to ask the engineer for confirmation.

Looking forward to your reply.

EngWei_O_Intel's avatar
EngWei_O_Intel
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4 years ago

Hi there

If we look at section "Differential I/O Pins" on page 5,6 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/arria-ii-gx/pcg-01007.pd...

it mentioned the pin convention for either true LVDS transmitter/receiver, then from the pin list files in this link (choose your used device):

https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html

look for the pin location that mapping the pin convention.

Let me know if you have further question.

Thanks.

Eng Wei

  • EngWei_O_Intel's avatar
    EngWei_O_Intel
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    4 years ago

    Hi there

    We do not receive any response from you to the previous reply that have been provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

    Eng Wei