New Contributor
Frequent ContributorThanks for your request.
Can you check if pin connection guideline doc may help?
And also you can refer to pinout list below on definition of each pin:
https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html
Thanks.
Eng Wei
New ContributorThank you for your reply.
I have read the two documents you sent. They are all about FPGAs, but our problem is mainly that we want to use the Seriallite II IP core and cannot confirm the connection between the signal and the FPGA pins. We are worried that the chip will be damaged during use, So I want to ask the engineer for confirmation.
Looking forward to your reply.
Frequent ContributorHi there
If we look at section "Differential I/O Pins" on page 5,6 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/arria-ii-gx/pcg-01007.pd...
it mentioned the pin convention for either true LVDS transmitter/receiver, then from the pin list files in this link (choose your used device):
https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html
look for the pin location that mapping the pin convention.
Let me know if you have further question.
Thanks.
Eng Wei
Frequent ContributorHi there
We do not receive any response from you to the previous reply that have been provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Eng Wei
