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1. i use the transceivers just to transmit the data in FPGA .
2. i setup the transceivers as described below:
a> Basic double-width mode
b> only 1 channel
c> operation mode is Transmitter only
d> channel width is 40 bits
e> input clk frequency is 200 MHz and lane rate is 4Gbps
f> Tx PLL bandwidth mode is Medium
other option is default
3. only have a Transmitter,so there is no ALTGX_RECONFIG block in the project
4. i have designed a reset controller to resets the ALTGX, just as described in “Transceiver Reset Sequences” of《Reset Control and Power Down in Stratix IV Devices》
5.i have finished the simulation in Modelsim SE 6.1,everything is all right,so it's confused me.
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It sounds like you have configured everything correctly.
Have you tried different data rates and clock sources to see if you get a different result? You can use a global clock to generate a PLL output that can then be used as the transmitter reference clock. For the purpose of debugging, this should be fine. It does work, as I have tried it on the Stratix IV GX development kit to change the 100MHz reference into a 156.25MHz reference.
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I Programming the same .sof in Stratix IV GX for many times.But the result is different ,sometimes the tx_clkout is right, sometimes tx_clkout is wrong,and the pll_locked is invalid.
in my opinion,it may be the problem of CMU,but i don't know how to change the project to let it be well.
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Are you sure your 200MHz reference clock is good? What about power supplies? Is this a custom board? Do you have an Altera reference board you can compare to.
Have you used SignalTap II to generate a trace of what happens near the time the PLL comes unlocked? For example, set a trigger on your reset controller at the end of the reset sequence, and ensure that all the timing looks like that in the handbook. Then, set another trigger for when the PLL unlocks. Perhaps the traces of the other control signals will tell you what could be wrong.
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by the way, if necessary, i can Email my project to you.
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Lets see how we go, and then if we cannot find a solution, I can try your design on the Stratix IV GX development kit to see if it works.
Cheers,
Dave
Honored Contributor
