the Transceiver IPcore in Stratix IV GX can't work well

thanks Dave

1. i use the transceivers just to transmit the data in FPGA .

2. i setup the transceivers as described below:

a> Basic double-width mode

b> only 1 channel

c> operation mode is Transmitter only

d> channel width is 40 bits

e> input clk frequency is 200 MHz and lane rate is 4Gbps

f> Tx PLL bandwidth mode is Medium

other option is default

3. only have a Transmitter,so there is no ALTGX_RECONFIG block in the project

4. i have designed a reset controller to resets the ALTGX, just as described in “Transceiver Reset Sequences” of《Reset Control and Power Down in Stratix IV Devices》

5.i have finished the simulation in Modelsim SE 6.1,everything is all right,so it's confused me.

ps: I Programming the same .sof in Stratix IV GX for many times.But the result is different ,sometimes the tx_clkout is right, sometimes tx_clkout is wrong,and the pll_locked is invalid.

in my opinion,it may be the problem of CMU,but i don't know how to change the project to let it be well.

by the way,if necessary ,i can Email my project to you .

thanks very much

best regards

flzhn