The need there I sjould use FFT instead of FIR (convolution)

Thank you very much, kaz!

So as I understand FFT is inefficient for filter design, what is the purpose for using fft megacore produced by altera?

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Thank you very much, kaz!

So as I understand FFT is inefficient for filter design, what is the purpose for using fft megacore produced by altera?

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to make money.

You will need it for some applications that required moving from time domain to frequency domain or vice versa e.g. cofdm mod/demod

We use the FFT for channelization of the spectrum. The core is now free with the subscription version of quartus. So if you have the subscription version, you can try it out.

If you are doing more than 5-10 channels the FFT will be the better solution. We are using it to do 127 channels.

Is it the most efficient resource for what you are doing? Don't know. but can it be done? Yes.

Pete

Thank you, Pete!

And why you don't use FIR? It also have multiple channels.

It will be very interesting if somebody will tell the way he use the core in practice.

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Thank you, Pete!

And why you don't use FIR? It also have multiple c

It will be very interesting if somebody will tell the way he use the core in practice.

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If I understood Pete:

For one signal you can do one fft first then for each channel (filter) you set its stopband to zero and do ifft per channel. So still plenty of resource and delay of framing fft/ifft.

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If I understood Pete:

For one signal you can do one fft first then for each channel (filter) you set its stopband to zero and do ifft per channel. So still plenty of resource and delay of framing fft/ifft.

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1) Framing delay can be reduced to zero by using tricky algorithm of convolution (based on dividing impulse response in parts). This article is about - http://www.cs.ust.hk/mjg_lib/bibs/dpsu/dpsu.files/ga95.pdf. But this algorithm (as i understood) is targeted for DSP processors foremost.

2) Resource utilization is more complicated problem. There are differerent ways of implementation of FFT in FPGA (i mean implementations of both methods - DIT/DIF and pipelined FFT), some of them expected to be more efficient than Altera IP Core. But in my opinion using FFT convolution in FPGA instead of FIR in case of low sampling rate of signal (relative to system clock) is not efficient way of using internal resources.

The system has multiple channels, that all need to be decoded simultaneously.

They are simple modulations, IE: AM, OOK, FM, GFSK, FSK, and although it can be extended to QAM, etc, the system doesn't require this yet.

The FFT is used to channelize the system. and the rest of the bit decoding is done in the frequency domain. There are some simple lowpass IIR filters used in the system, but the maximum clock rate is not as high as what would be required to do true FIR filters for 127 channels. (Either need lots of multipliers, or to run the multipliers extremely fast.)

For the simplest case, AM/OOK, the output of the Real and Imaginary output of the FFT is going through a square root function to give magnitude. This is based through a low pass filter giving a slow DC average. This passes through a bit slicer giving 1's and 0's that then pass into a correlator looking for the sync word of the incoming packet. Since I'm decoding in the frequency domain, I'm not filtering in the typical sense. I have worked on systems in the past where a FFT is performed, bins are masked, then an IFFT is performed, but that was used for a system where they need the time domain back, but wanted to apply a complex comb filter.

Pete

Thank you, Pete!

So in your application it is effecient to use FFT because of lower frequency compared to FIR filters-based system?