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If I understood Pete:
For one signal you can do one fft first then for each channel (filter) you set its stopband to zero and do ifft per channel. So still plenty of resource and delay of framing fft/ifft.
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1) Framing delay can be reduced to zero by using tricky algorithm of convolution (based on dividing impulse response in parts). This article is about -
http://www.cs.ust.hk/mjg_lib/bibs/dpsu/dpsu.files/ga95.pdf. But this algorithm (as i understood) is targeted for DSP processors foremost.
2) Resource utilization is more complicated problem. There are differerent ways of implementation of FFT in FPGA (i mean implementations of both methods - DIT/DIF and pipelined FFT), some of them expected to be more efficient than Altera IP Core. But in my opinion using FFT convolution in FPGA instead of FIR in case of low sampling rate of signal (relative to system clock) is not efficient way of using internal resources.
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