Occasional ContributorHi,
We are using the fPLL Intel Arria 10 FPGA IP, the input reference clock is set to 100MHz, PLL output frequency is set to 2GHz, as shown in the attached screenshot.
However, we found the actual PLL output frequency seems to be only up to 1.6GHz, and sometimes the lock signal of fPLL isn't locked.
So, is the max output frequency 1.6GHz?
Thanks in advance.
Regular ContributorHi,
You are right.
The PLL max output frequency is limited by the VCO frequency which is 1.6GHz. Please refer the datasheet for IOPLL specifications:
Regards
Occasional ContributorHi,
Thanks for your reply.
However, we are using fPLL, but not the IOPLL, we refer to Fractional PLL Specifications (attched image here), the max frequency is 14GHz.
Are the fPLL and IOPLL have the same specifications?
Regular ContributorHello,
For the FPLL in Transceiver mode, refer datasheet table 22:
As per this, the maximum output frequency that a fpll can drive is 6.25 GHz.
Please note, that the VCO frequency is not directly available at the output of the fpll. Refer, the architecture diagram in below link:
https://www.intel.com/content/www/us/en/docs/programmable/683461/current/pll-architecture.html
From the datasheet table, always refer the parameter fout for the maximum frequency that can be driven by a pll.
For, your lock issue, probably there is some other reason like input clock signal integrity or termination etc. to loose the lock.
Regards
