The max output frequency of fPLL Intel Arria 10 FPGA IP

Hello,

For the FPLL in Transceiver mode, refer datasheet table 22:

https://www.intel.com/content/www/us/en/docs/programmable/683771/current/transceiver-performance-for-gx-sx-devices.html

As per this, the maximum output frequency that a fpll can drive is 6.25 GHz.

Please note, that the VCO frequency is not directly available at the output of the fpll. Refer, the architecture diagram in below link:

https://www.intel.com/content/www/us/en/docs/programmable/683461/current/pll-architecture.html

From the datasheet table, always refer the parameter fout for the maximum frequency that can be driven by a pll.

For, your lock issue, probably there is some other reason like input clock signal integrity or termination etc. to loose the lock.

Regards