Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

TG > VCO > SDI IP block issue

I have a simple test design that consist of only three IP blocks. Using Quartus 9.1, and here is the problem I can't figure out what causing it. test1: TG (720x486, 10bit sequence, interlace...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Test1 does not work because the CVO is expecting F0=244 lines and F1=243 lines in this case. The Test Pattern Generator cannot produce this sequence. You can work around this issue as follows:

TG (720x487, 10bit sequence, PROGRESSIVE) >> Interlacer >> VCO (preset to ntsc)