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Altera_Forum
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9 years ago

Test Pattern Generator -> Clocked Video Output with Altera NEEK

I have an Altera FPGA NEEK and I want to use the following VIP cores setup: CVI(Clocked Video Input) -> SCL(Scaler) -> FB(Frame Buffer) -> CVO(Clocked Video Output). This gives me a screen with ve...
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Altera_Forum
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9 years ago

Found the solution. Thanks for your help ted Altera Guru!

TPG->TimingAdapter->VideoSyncGenerator works, but the screen keeps blinking.

Fixed this by using the VIP core ClockedVideoOutput: TPG->CVO and then set the lcd_video_interface values in Verilog .v.

Now I have color bars on my Altera NEEK's screen!