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Altera_Forum
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10 years ago

Test Pattern Generator -> Clocked Video Output with Altera NEEK

I have an Altera FPGA NEEK and I want to use the following VIP cores setup: CVI(Clocked Video Input) -> SCL(Scaler) -> FB(Frame Buffer) -> CVO(Clocked Video Output). This gives me a screen with ve...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

How do I connect CVO to SGDMA?

I followed the System Architecture Tutorial of PictureViewer and have something working where it takes pictures from a SD card and using the following IP Cores (SGDMA->TimingAdapter->FIFO->TimingAdapter->FormatAdapter->PixelConverter->FormatAdapter->VideoSyncGenerator) to load the pictures on the LCD screen of my NEEK.

There is no connection dot for a TPG or CVO to connect to the SGDMA. Am I missing another IP Core?