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Honored Contributor
Honored ContributorTest Pattern Generator -> Clocked Video Output with Altera NEEK
I have an Altera FPGA NEEK and I want to use the following VIP cores setup: CVI(Clocked Video Input) -> SCL(Scaler) -> FB(Frame Buffer) -> CVO(Clocked Video Output). This gives me a screen with ve...
Altera_ForumHonored Contributor
Honored ContributorIn the latest documentation for Test Pattern Generator II IP Core, they included a screenshot of the test image.
See https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_vip.pdf
