[Test] Agilex 5 TX PLL sharing

What is the maximum number of system PLL in Agilex 5 device? Also, does Agilex 5 XCVR go by tile?

Good question — let me clarify how TX PLL sharing works in the Agilex 5 GTS transceiver architecture, because the TX PLL and the System PLL play distinct roles here.

TX PLL — No sharing needed (or possible) across channels

In Agilex 5, each channel has its own TX PLL, and one system PLL is available per bank. Agilex 5 · Config/RSU Because of this per-channel TX PLL architecture, no TX PLL sharing is required across channels. If multiple channels use the same rate, each channel is driven by its own TX PLL sharing the same REFCLK source. Agilex 5 · Config/RSU So the concept of "sharing a TX PLL between PCIe and non-PCIe channels" doesn't apply — each channel independently owns its TX PLL.

The real restriction is on the System PLL

The constraint you need to watch is at the System PLL level, not the TX PLL level. Each GTS transceiver bank has one system PLL, which is the primary clock source for hard IP blocks (Ethernet MAC, PCS, FEC, and PCIe) and the core interface bridging the FPGA core and the GTS transceivers. Agilex 5 · Clock

The critical rule: different interface protocols operating at different line rates can share a system PLL, except for PCIe. Agilex 5 · Clock

This means if you need both PCIe and non-PCIe protocols in the same GTS transceiver bank, and both require a system PLL, you must use two system PLLs. Since there is only one system PLL in a GTS transceiver bank, a second or third system PLL can be used from the neighboring GTS transceiver banks. Agilex 5 · Clock

A concrete example from the docs: if channels 0 and 1 in GTS transceiver bank 1A are configured for PCIe, and channels 2 and 3 are configured for Ethernet, then the system PLL in GTS transceiver bank 1A can be configured for PCIe, and the system PLL from GTS transceiver bank 1B can be configured for Ethernet. Running PCIe® and Non- PCIe® Protocols in a GTS Transceiver Bank

Additional bonding rule

If you are bonding multiple lanes to a single link, there is one more constraint: when bonded channels use a system PLL, they must all use the same system PLL. Agilex 5 · Transceiver/PHY

PCIe reference clock timing

There is also a timing requirement specific to PCIe: PCIe must have its system PLL's reference clock ready by the time of device configuration for PCIe link-up compliance. Agilex 5 · PCIe This is an exception to the general reference clock availability model.

Summary

• TX PLL: one per channel, no sharing across channels — the question of PCIe vs. non-PCIe TX PLL sharing doesn't arise.


• System PLL: PCIe cannot share the system PLL with non-PCIe protocols. You must use a separate system PLL (borrowed from a neighboring bank) for the non-PCIe side.


• Bonded channels using a system PLL must all use the same system PLL.