Forum Discussion
New ContributorTechnical Inquiry regarding DPCU Block for CPRI IP Single-Trip Delay Calibration
I am currently implementing the "single-trip delay calibration" feature using the Intel CPRI IP core.
According to the User Guide (ID: 683595, Version: 2021.11.11), this feature requires the Dynamic Phase Control Unit (DPCU) block. The documentation states that "Intel provides the DPCU block with the CPRI IP." However, I am having difficulty locating this specific module.
Could you please clarify where this DPCU block is located or how it should be instantiated?
My design environment is as follows:
- Quartus Prime Version: 20.4 Pro
- Device Part Number: Arria 10 (10AS032H2F34I2SG)
- CPRI IP Version: 19.4.0
- Reference Document: CPRI Intel FPGA IP User Guide (ID: 683595)
Best regards!
7 Replies
CheepinC_alteraRegular Contributor
Hi,
Thank you for your inquiry regarding the Dynamic Phase Control Unit (DPCU) module referenced in the CPRI IP User Guide.
To provide you with an update, I have attempted to generate the CPRI IP example design; however, I was unable to locate a distinct DPCU module within the generated deliverables. I am currently following up internally with the factory team to clarify the availability and access method for this module.
I will keep you informed on the progress by end of next week or as soon as I receive a valid update from them. In the meantime, please feel free to reach out if you have any additional questions or if you do not hear back from me.
Thank you for your patience and understanding.
KangdiThank you very much for your explanation! Looking forward to your update.
- CheepinC_altera
Hi,
I’d like to share an update based on a response from the factory team. They have confirmed that the DPCU block is packaged within the CPRI IP, and it can be instantiated directly at the top level using the pll_dpcu module. This can then be connected to the IO PLL as needed.
Below is an example of how the instantiation would look:
pll_dpcu #(
// parameters
) pll_dpcu_inst (
.clk (clk),
.reset_n (rst_n)
// ...
);
I’ve tested this instantiation on my side and confirmed that the module appears correctly after Analysis & Synthesis in Quartus completes.
Please try this approach and let me know how it goes, or if you have any questions or issues along the way.
Thank you.
- CheepinC_altera
Hi,
Thank you for filing this case and sharing the details. I appreciate your patience. Please allow me some time to review the information, and I’ll get back to you as soon as possible.
