TCP/IP Offload Engine Implementations -- What's the big deal?

Hi all,

I've recently begun a project where I have to build a TCP/IP offload engine (maintain at least a few dozen TCP sessions; calculate checksums, maintain some state for each, retransmission buffers, etc. etc.). Basically, the IP core will accept standard, "uninterrupted" (read "buffered") Avalon-ST like interfaces for transmission and receipt of data, but manage a full TCP link within itself, seamless to the user(s) of the interface.

Of course, my first inclination was to look for IP out there for sale which will easily port to and work on the Altera device I am targeting (a Stratix V chip). To my dismay, most of these IP cores are actually quite expensive! What's the big idea? It really seems to me like an experienced FPGA developer would be able to build a TCP offload engine within a few months time, and the market competition + number of purchasers of such an IP core would warrant making the price lower than several tens of thousands of USD.

From my perspective, one would only have to maintain a few retransmission buffers, some session state information (directly mapping to each of the states documented in the TCP specs), tack on the appropriate stuff to the headers (a la UDP; except for things like window sizes and sequence numbers); I understand it's not totally trivial, but am I missing something crucial here? Before I set out to build this: has anyone here worked on a TCP or similar engine in Verilog/VHDL? What were the biggest hurdles? Why would this be any more complicated than something like a PCI Express IP core? Are there any IP cores which Altera offers which support a protocol that is similar to TCP and solves some of the same fundamental problems (retransmission buffers; windowing; etc)?