Forum Discussion

Honored Contributor

15 years ago

system with DDR2 HPCII can't meet timing requirement!

Hi In my project, i add a DDR2 HPCII to my system, after compilation, the timming meets my requirement. while after adding a second module to the previous system, the timing no longger meets. ...

Altera_Forum

Honored Contributor

15 years ago

A pipeline bridge in front of the memory should help. I would recommend skimming through this document to learn more about where to place the bridges especially if you have hooked up a lot of masters to the memory: http://www.altera.com/literature/hb/nios2/edh_ed51007.pdf

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system with DDR2 HPCII can't meet timing requirement!

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