Hallo I'm a student of the univerity o Zurich (Switzerland) and I develop a mp3 encoder/decoder on a Dev Board DE2 Cyclone 2 with EP2C35F672 fpga. The synthese on dsp-builder do not work, I became a errore message "Out of memory 4200 MB". My workstation have x64 OS Windows 7 Prof with 8GB RAM. Can I make settings in DSP-Builder for correct mapping with RAM? Wath for features have the Quartus V9.1 with DSP-Builder V9.1? Does this Version 9.1 work better with RAM-mapping? Thanks you.

it is actually pretty strange seeing out of memory targeting a CII device. i will take a look at your mdl.

i ran your model from the other thread. i changed clock_1.536MHz to clock_1536MHz, and unchecked the specify clock boxes in all of the blocks which used clock_1536MHz just to get it to compile. i was able to successfully run all the way through Signal Compiler's compile, though it did use a ton of RAM.

i am using MATLAB 2008b and Quartus II/DSP Builder 9.1

thank you for try a simulation on your pc. I have changed my mdl-file, could you test this new file on your pc again? I became the same error "out of memory 4200GB", that's strange... I use Matlab 2009b, quartus 9.0 and dsp-builder 9.0. I have both quartus x32 and x64 on my pc, but is not the OS Win7 x64 that managed the mapping with RAM's? Best regards...

I found the failure, I has insert a bus conversation on the output from my IIR with "signed int 16-bit in/out and make settings in DPRAM also signed int 32x16 bit and not inferred. The reason was, I has to large information with always inferred settings, but is not important at the output from my IIR, when the signal is 205.12584 or only 205. Now the consuption of my RAM are about 1200MB... Thanks...

Synthese failed on DSP-Builder "Out of Memory 4200MB"

22 Replies

Altera_Forum
Honored Contributor
16 years ago
I've now checked your MDL file and I can confirm that the MDL file has this problem as well. (To see the bit widths click the "Format" menu, follow "Port/Signal Displays" and select "Port Data Types".

Your IIR_Block subsystem has inputs of type SBF_1_18, which means 1 bit left of the binary point and 18 points to the right. Its output has type SBF_4436_4608, which you then reduce down to a 16 bit integer.

The problem mostly seems to stem from you using Inferred as the Bus Type. The inferral seems quite wrong. For Gain_1, you have INT_16 (bitwidth 16) X SBF_1_18 (bitwidth 19) = SBF_32_36 (bitwidth 68), when it should be SBF_17_18 (bitwidth 35).

As a short term fix I would try not using "Inferred", but manually inputting the width.
Altera_Forum
Honored Contributor
16 years ago
nice debugging, certainly explains why a CII design ran out of memory.

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Synthese failed on DSP-Builder "Out of Memory 4200MB"

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