Forum Discussion
Altera_Forum
Honored Contributor
16 years agoLooking at the VHDL, I think the problem is that the bit widths in your design are huge. Looking at alt_dspbuilder_product_GNWK6HVYWC.vhd, you have a multiplier with inputs of size 9044 and output of size 18088 and with a pipeline length of 0.
Is that intended? Do you have that in the MDL file as well? (I'll try harder to get DSPB over here so I can stop asking questions soon)