Suppress every third clock pulse

Kaz's suggestion is probably the best. It's not really recoding for three states, it's just disabling the slower registers for one clock cycle(and the logic would be pretty similar to what you're creating for the altclkctrl block, except it would be localized to your logic). Note that if you had the clock you asked for, your sysem would still need some correlation logic, as there's no way it knows the longer pulse is for the instruction and the shorter one for the fetch. On different power-ups you would have it occur differently each time. With a clock enable, you have direct control over it.