Suppress every third clock pulse

Thanks for the quick response. I will restate my problem; I have coded a simple non-pipelined CPU that uses only two states/instruction: fetch and execute. Now that I have it running at 100 MHz (50 MIPS, 10 nsec/state), I found the fetch cycle can be shortened to 5 nsec. Recoding the CPU for three states in an unpleasant option. I guess the best way is to start with a 200MHz clock, and write a simple 3 state machine that generates an asymetrical CPU clock, and feed this through the altclkctrl block.