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alexislms's avatar
alexislms
Icon for Contributor rankContributor
3 years ago
Solved

Support logic conflicts with F-tile PMA clocking and double-width 16b (Quartus Pro 22.1)

I tried to set the F-tile: PMA Direct PMA clocking PMA width 16b TX and RX double-width enabled Qsys doesn't complain and I can generate the files. From the user guide, it seems poss...
Kshitij_Intel's avatar
Kshitij_Intel
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi,


You can change the width to 32 from 16 in the F-Tile PMA/FEC Direct PHY Intel FPGA IP and then it will get compiled. Sharing the screenshot.



Thank you

Kshitij Goel