Forum Discussion
alexislms
Contributor
ContributorSupport logic conflicts with F-tile PMA clocking and double-width 16b (Quartus Pro 22.1)
I tried to set the F-tile:
PMA Direct
PMA clocking
PMA width 16b
TX and RX double-width enabled
Qsys doesn't complain and I can generate the files.
From the user guide, it seems poss...
Using the F-tile clocking tool excel file (https://community.intel.com/t5/FPGA-Intellectual-Property/F-tile-excel-file-Error-Page-Not-Found/m-p/1394117#M25857)
Kshitij_Intel
Frequent Contributor
Frequent ContributorHi,
You can change the width to 32 from 16 in the F-Tile PMA/FEC Direct PHY Intel FPGA IP and then it will get compiled. Sharing the screenshot.
Thank you
Kshitij Goel
