Stritix IV + DDR3 controller write unstable

Question

ENV: stritix IV + altmemphy DDR3 controller.

DDR write is sometimes unstable.

I used signaltap to observe signals of local bus.

I perform 2 experiments as the following.

1.When I stop writing DDR and read the same address.

the value from DDR is stable. This proved that DDR read is stable

2.When I start writing DDR and read that address, the value are sometime unstable, serveral bits are wrong.

any idea about the error ?

thanks.

altera_forum · Answer

You sure the hardware is OK? All terminations are fine? Is this happening, when tested on development kit?

altera_forum · Answer

&gt;You sure the hardware is OK? yes, I think hardware is OK. I use the following S4 Tai logic module. please google "S4 TAI Logic Module" I cannot post links right now.   &gt;All terminations are fine? Hardware terminations or pin setting ?   &gt;Is this happening, when tested on development kit ? Not on development kit, it's on my code. I used signaltap to observe signals of local bus. the signals satisfied the protocol.

altera_forum · Answer

So You're not using UniPHY?

altera_forum · Answer

--- Quote Start ---  So You're not using UniPHY?  --- Quote End ---   No, I use altmemphy.

altera_forum · Answer

Why? UniPHY is a great controller. Plus You'll get information about it's calibration and all the stuff through JTAG.

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Stritix IV + DDR3 controller write unstable

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