New Contributor
Regular ContributorHi
Which PHYLite table that you referred to? Can you provide the link to the that?
The simulation run is with a design that has NIOS + Address Span Extender + PHYLite IP?
It's possible to debug this issue without using Address Span Extender?
Maybe can try to reduce the number of group in PHYLite IP?
How do you enable the Avalon Memory Mapped Slave in PHYLite IP?
Regards,
Adzim
New ContributorHi,
My intention is to read parameter table which you can refer in these documents. You can also go through this data sheet for further information regarding it.
https://www.intel.com/content/www/us/en/docs/programmable/683716/20-3/introduction.html
Figure 33 in this document.
https://www.intel.com/content/www/us/en/docs/programmable/683220/current/reference-design-with-dynamic-reconfiguration.html
Figure 23 in this document.
This design, which includes the Nios processor, Address Span Extender (ASE) IP, and PHYLite IP, is intended for on-board testing.
I used the ASE IP because the Nios II processor supports only upto 32b.
To enable the Avalon Memory-Mapped interface in the PHYLite IP, I have configured the IP with dynamic reconfiguration enabled.
