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rkv's avatar
rkv
Icon for New Contributor rankNew Contributor
5 years ago

Stratix10 P-Tile AVMM IP for PCIe does multiple read requests for a single s/w 64-byte read request

The software is able to do 64-byte single read transaction to on-chip ram by making the BAR region as WC region using the instruction below. __m256i a = _mm256_stream_load_si256 ((__m256i*)mem_base...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


Just to clarify, please do let me know if my understanding is correct:


  1. 64 Bytes single read from Host to the FPGA endpoint (On-chip memory)
  • A single read was observed, where the readdatavalid and *_m_read_o only asserted once
  1. 64 Bytes single read from Host to FPGA endpoint (Customer component)
  • Three single reads were observed, where the readdatavalid and *_m_read_o asserted three-time
    • All three read are read out at the same address with the same data


To further understand the problem, could you please also capture the Avalon-ST interface, this can further help to identify whether the host is sending three memory read request continuously?


You should be able to add the tx_st* and rx_st* signal into the signal tap.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ptile_pcie_avst.pdf


Regards -SK


rkv's avatar
rkv
Icon for New Contributor rankNew Contributor
5 years ago

Your understanding is correct. We are using AVMM interface and the screenshot of the same is attached already. In that screenshot you can see that immediately after read_data_valid is asserted from the FPGA custom component, read is again asserted by PCIe P-Tile IP.

Also please note that the FPGA custom component asserts read_data_valid after some time. So does this has any impact? We also tried with 32B Read transaction and didn't face any issue.