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Altera_Forum
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11 years ago

Stratix V PCIe HIP not supporting Avalon MM Gen3 x8 I/F

Can anyone say why ? I have a single EP design using Avalon MM interconnect and across Cyclone IV, Arria V and Stratix V and I want to support Gen3 X1, X4 and X8 on the Stratix V card ... Th...
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Altera_Forum
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10 years ago

Instead of rely on assign gen3_speed = tl_cfg_tl_cfg_sts[32:31] == 2'b11;

how about you use Signaltap II to monitor current_speed[1:0] and see if the link is really train-up to gen3.

The following encodings are defined:

- 2b’00: Undefined

- 2b’01: Gen1

- 2b’10: Gen2

2b’11: Gen3