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Altera_Forum
Honored Contributor
Honored Contributorstratix iv qdr_sram_compiler_wirh uniphy
hello, Now I'm using stratix iv 230 device in a project.I use qdr_sram_compiler_with_uniphy as my qdr2 chip controller.The software is quartus ii 10.0 sp1.All the docs downloaded from the web do n...
Altera_ForumHonored Contributor
Honored ContributorBurst length is number of accesses per command.
Take DDR3 which is nominally BL=8 on the memory interface. If using half rate I need to provide 2 beats of data to get the entire 8 beats on the memory interface. If I do this on consecutive clock edges I can set local_size = 2 and set burstbegin high on the first one. Or if the data is not ready on consecutive clock cycles I can use local size = 1 and push the first beat in, wait and do the same again for the 2nd beat, each time setting burstbegin high.
