Honored Contributor
Honored Contributorhi,std_logic.
At the first sight of your name,i see the you are expert on VHDL.Yes?Haha,just a joke. Based on several experiments,I have summarized the usage of avl_w_write_size.Max_burst_length affects the width of avl_w_write_size(also avl_read_size),Nwidth = (log 2 (max_burst_length))+1.What is burst length?Cycpress's qdrii chip generally has 2 or 4 mem array,ie the data width of the chip is 9,addr width is 21.There 2 or 4 mem array with 21 addr width and 9 data width.If the burst_length is 2,then the avl_write_data and avl_read_data is 18,or if the burst_length is 4,then the avl_write_data and avl_read_data is 36.Here burst_length is not the same as max_burst_length. What is the usage of "size"?For example,we set max_burst_length is 8.Then the width of "size" is 4.If we set "size"="0001",when read and write,we should increase the address by a0;if we set "0010",we should increase the address by a1;if we set "0100",we should increase the address by a2;if we set "1000",we should increase the address by a3.A3,pay attention to it,burst = 8 words. All above is summarized by experiments,docs about the new ip is like noting.I have consulted to altera FAE,but they do not kown it very well.Hope docs released!!
