Stratix IV DDR3 memory controller with Unify : simulation not working

I have seen this too. It is a bit messy to use their simulation IPs. The code of the IP assumes you have your RTL/IP files in the same directory you simulate, what I believe is a mistake. I then change one file to point to the correct location. This is a problem as every time the IP is regenerated the code has to be repatched, but at least we keep some kind of order.

After the IP files have been generated we generate the simulation files by:

From the directory .../mem_ip/simulation/ use quartus_sh -t generate_sim_verilog_example_design.tcl

And then edit the file syn/sm01/mem_ip_sim/mem_ip/mem_ip_s0.v and then add IPHEXDIR to the parameters: INIT_FILE, AC_ROM_INIT_FILE_NAME, INST_ROM_INIT_FILE_NAME.

At the end each has to be: ({`IPHEXDIR, “.......”}).

Then when I simulate I pass a define via the command line for IPHEXDIR. This could have been statically written but with it dynamic makes it easier to move the code around in case we need to.

For the command line, I simply copied out the libraries defined in the cadence shell script. Then we run it in our environment.